Multicore: More Moore or Multi Trouble?

Chair:

Dr. Erich Strohmaier, Head of Future Technology Group, Lawrence Berkeley National Laboratory (LBNL), USA

A fundamental change in computing took place around late 2004. Intel followed the lead of IBM’s Power 4 and Sun Microsystems’ Niagara processor in announcing that its high performance microprocessors would henceforth rely on multiple processors or cores. The new industry buzzword “multicore” was born. Moore's law will continue, and we will see for maybe another decade a doubling of transistors per chip every 18 months or so. But "More Moore" from now on means something completely different for the industry: a doubling of the number of cores per chip, and thus the inevitable introduction of parallelism into all aspects of computing.

For more than three decades researchers concerned about a high-end computing have been fascinated by parallelism, and for more than a decade virtually all high-end system have been parallel. But in spite of the long lead time, the HPC community has not yet been able to achieve breakthrough results mastering parallelism. There are hardly any good tools out there to make parallelism obvious, or to hide it, or to automatically generate parallel programs. Even for applications where we do know how to parallelize them, the development of actual parallel code (most likely in MPI) is something done by only a few experts. Given that unsatisfactory state of parallel programming models and software, the prospect of the whole computing community embracing multi-core appears to bring multi-trouble for the industry.

Uncertain times are ahead of us, and this time it is not just the small HPC segment of the computer market that is concerned about a fad, but the issue of multi-core will impact everyone. In this session at ISC09 two experts who have both a long history of research involvement with parallelism will present their views on the potential future developments in hardware and software. Yale Patt is Professor of Electrical and Computer Engineering and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin. Today, Yale Patt works on problems for the microprocessors of the year 2015, when technology promises each chip will contain more than ten billion transistors. Kathy Yelick is the Director of NERSC, and Professor of Computer Science at the University of California, Berkeley. Kathy Yelick has devoted her career to making parallel machines easier to use through the use of libraries, languages, compilers, and other software tools. In this session the two experts will explore some of the most important questions that the HPC community is asking itself today: What will future multi-core and many-core systems look like? Will we have homogenous or heterogeneous systems? Will there be a standard architecture like x86, or will hundred flowers bloom? Will we be using MPI on these systems? What alternative programming models will be out there? Will there be industry solutions that will overtake HPC? Or will the HPC community and ideas invade the world of computing research? And finally ... how will we effectively use a 10 million core supercomputer?