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Dr. Frank Baetke, Global HPC-Technology Program Manager, Hewlett-Packard
Abstract
Future Challenges for HPC
Dr. Rudolf Fischer
Chief Technology Officer HPCE
NEC, Germany
NEC has a track record not only as the world-leader in vector computing, but also as a company that can provide the right tool for every HPC-requirement, from scalar clusters made from commodity components over SMP-servers, which are based on commodity with some add-on, to the high-end vector. NEC will keep this general direction.
TCO is becoming the dominant aspect of HPC, and the notion of price/performance is consequently changing. For evaluation the purchase price plus running costs over the duration of the project will be balanced against the sustained performance of the offered system.
In addition the effort to achieve good performance, and thus price/performance, on real codes will be taken into account as a cost impact. There are challenges: forthcoming clustered SMP-systems with multi-core-chips require not only optimisation for a single core, but also an efficient utilisation of many cores with a shared cache by fine-grain shared memory parallelisation, beyond that on a second level of parallelisation the SMP-characteristic with NUMA in mind, and beyond that distributed memory programming. This is the major challenge for the user in the future.
What does it take then? Sustained efficiency of the hardware is a basis. Memory architectures, memory hierarchies and sustained memory performance will become dominant in evaluations, but also regarding cost. Strong single cpus will make a difference at a time when new generations of chips will not provide for the automatic performance gain that the market was used to in the past, and when applications do not exhibit scalability as it is found in some special applications. Hybrid parallelisation strategies are inevitable, leading to the need of strong SMP-nodes.
On the vector side the NEC SX-9 is already successful now, future generations of NEC vector products will continue and be targeted to even better address TCO, to find the optimal balance between price and performance.
TCO is becoming the dominant aspect of HPC, and the notion of price/performance is consequently changing. For evaluation the purchase price plus running costs over the duration of the project will be balanced against the sustained performance of the offered system.
In addition the effort to achieve good performance, and thus price/performance, on real codes will be taken into account as a cost impact. There are challenges: forthcoming clustered SMP-systems with multi-core-chips require not only optimisation for a single core, but also an efficient utilisation of many cores with a shared cache by fine-grain shared memory parallelisation, beyond that on a second level of parallelisation the SMP-characteristic with NUMA in mind, and beyond that distributed memory programming. This is the major challenge for the user in the future.
What does it take then? Sustained efficiency of the hardware is a basis. Memory architectures, memory hierarchies and sustained memory performance will become dominant in evaluations, but also regarding cost. Strong single cpus will make a difference at a time when new generations of chips will not provide for the automatic performance gain that the market was used to in the past, and when applications do not exhibit scalability as it is found in some special applications. Hybrid parallelisation strategies are inevitable, leading to the need of strong SMP-nodes.
On the vector side the NEC SX-9 is already successful now, future generations of NEC vector products will continue and be targeted to even better address TCO, to find the optimal balance between price and performance.
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